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Earlgrey-M2.5.2-RC0

lowRISC/opentitan

版本发布时间: 2023-06-29 18:44:46

lowRISC/opentitan最新发布版本:Earlgrey-PROD-M5(2024-08-12 22:39:11)

Overview

This is the EarlGrey Engineering Sample release candidate. All blocks are at least at D2.5 design stage, and V2.5 verification stage (except for RV_DM, USBDEV, PWM and PATTGEN).

This release is associated with GitHub milestone: M2.5.2

D2.5 versus D3

D2.5 is strictly a subset of the D3 signoff criteria, including the following D3 checklist items:

  1. Meets D2(S) signoff criteria
  2. Meets D3 signoff criteria for the following items:
    1. TODO_COMPLETE
    2. LINT_COMPLETE
    3. REVIEW_RTL
    4. REVIEW_SW_CHANGE
    5. REVIEW_SW_ERRATA

D2.5 reviews were performed offline and are tracked in checklists available in OpenTitan.org internal documents.

V2.5 versus V3

V2.5 is strictly a subset of the V3 signoff criteria, including the following V3 checklist items:

  1. Meets V2 or V2S signoff criteria
  2. DESIGN_DELTAS_CAPTURED
  3. ALL_TODOS_RESOLVED
  4. TB_LINT_COMPLETE
  5. PRE_VERIFIED_SUBMODULES
  6. NO_ISSUES_PENDING

V2.5 coverage metrics are at V2S level, and thus not referenced in the list above. Signoff reviews were performed offline and are tracked in checklists available in OpenTitan.org internal documents.

Release Contents

Design

All IPs meet the D2.5 development stage requirements:

  1. D3 (14 of 35): lc_ctrl, uart, otp_ctrl, sysrst, adc_ctrl, alert_handler, aon_timer, gpio, pinmux, rom_ctrl, rv_plic, rv_timer, sensor_ctrl, sram_ctrl
  2. D2.5 (21 of 35): All other blocks

Design Verification

All IPs are at V2.5 level, except for the IPs which have a verification signoff waiver (USBDEV, RV_DM), or which are explicitly not required to fully work for the ES tapeout (PWM, PATTGEN).

The following section notes the progress that has been made towards the M2.5.2 goal.

  1. V2.5 (31 of 35): usbdev, i2c, rv_dm, entropy_src, spi_device, spi_host, csrng, flash_ctrl, kmac, lc_ctrl, sysrst_ctrl, keymgr, edn, otp_ctrl, uart, tlul, otbn, sram_ctrl, rv_core_ibex, clkmgr, pwrmgr, rstmgr, adc_ctrl, alert_handler, aes, aon_timer, hmac, rom_ctrl, rv_timer, rv_plic, gpio, sensor_ctrl, pinmux
  2. V1 (1 of 35): RV_DM
  3. V0 (1 of 35): USBDEV
  4. V2S (2 of 35): pwm and pattgen
    Note that PWM and PATTGEN are functionally not needed for ES, since the use cases under consideration do not make use of these blocks.

Block Level Issues

  1. All block level issues assigned to M2.5.2 have been resolved.

Top Level Test Cases

  1. All Chip-Level test cases assigned to M2.5.2 have been resolved.
  2. All Test-Triage issues identified for M2.5.2 have been resolved.

Manufacturing

  1. All Manufacturing test cases assigned to M2.5.2 have been resolved.

Integration Testing

The following integration tests have been implemented and are passing:

  1. USB. Block level smoketest #18063. FPGA targeted testing.
  2. SPI_HOST. FPGA targeted testing. #18640
  3. SPI Passthrough. FPGA targeted testing #18320.
  4. I2C host. FPGA targeted testing. #18639
  5. I2C device. FPGA targeted testing #18541.

Coverage Assessment

All blocks are at the required 90% coverage level or above, with the exception of the following blocks:

  1. RV_DM: (Pass rate) 71.67, (Coverage) 81.52
    1. Implications are known and mitigation strategies as documented in the M2 waiver document available in the opentitan.org partner domain.
    2. An updated waiver document will be available as part of the M2.5.2 milestone that focuses on DV closure.
  2. USB_DEV: (Pass rate) 48.79, (Coverage) 76.36 3. Implications are known and mitigation strategies as documented in the M2 waiver document available in the opentitan.org partner domain. 4. An updated waiver document will be available as part of the M2.5.2 milestone that focuses on DV closure.

CDC and RDC Assessment

Static RDC analysis and dynamic CDC enablement in simulation have been worked on on a best effort basis. The current status is: \

Static CDC analysis was clean a few days before the release, but has now regressed to 7 setup warnings and 67 analysis errors due to last minute fixes to the spi_device RTL and updates to the spi_device synthesis constraints. The static analysis environment has not been cleaned up as part of M2.5.2 due to resourcing and tooling constraints. However, dynamic CDC has progressed well and 39 of 43 simulation environments now use CDC randomization.

Known Issues

The following known issues will not be addressed in the design and will require software workarounds.

Difference Among Release Candidates

Only one release candidate available for this milestone.

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