Version 1.6.0

Added

• Support for Chisel 3.5.3 (https://github.com/chipsalliance/rocket-chip/pull/2931, https://github.com/chipsalliance/rocket-chip/pull/2937, https://github.com/chipsalliance/rocket-chip/pull/2947, https://github.com/chipsalliance/rocket-chip/pull/3005)
• Support for Scala 2.12.15 (https://github.com/chipsalliance/rocket-chip/pull/2947)
• Properly-sized don't cares for FPU typeTag fields (https://github.com/chipsalliance/rocket-chip/pull/2949)
• Add a virtual argument to TLBEntry.sectorHit function (https://github.com/chipsalliance/rocket-chip/pull/2952)
• Support building PTW with no PTECache (https://github.com/chipsalliance/rocket-chip/pull/2962)
• Update IncoherentBusTopology to support multiclock and custom clocking (https://github.com/chipsalliance/rocket-chip/pull/2940)
• Allow forcing RocketTiles into separate PRCI groups (https://github.com/chipsalliance/rocket-chip/pull/2842)
• Add a WithHypervisor config (https://github.com/chipsalliance/rocket-chip/pull/2946)
• Add ScalaDoc documentation for I$ (https://github.com/chipsalliance/rocket-chip/pull/3001)

Changed

• AHPParameters and APBParameters:
  • PROT_PRIVILEDGED - This was a typo. It is now PROT_PRIVILEGED. (https://github.com/chipsalliance/rocket-chip/pull/2925)
• GrountTestTile: use generic BuildHellaCache key (https://github.com/chipsalliance/rocket-chip/pull/2919)
• copy EICG wrapper from vsrc when using Clock Gate Model (https://github.com/chipsalliance/rocket-chip/pull/2969/)
• PTW page fault instead of access exception if PTE reserved bit set (https://github.com/chipsalliance/rocket-chip/pull/2913, https://github.com/chipsalliance/rocket-chip/pull/2934)
  • PTE_RSVD was introduced into Spike in riscv-software-src/riscv-isa-sim#750
  • Reserved PTE bits report page fault instead of access exception.
  • Add an additional bit pf to PTWResp and TLBEntryData to pipe this through.
• Have HFENCE.GVME sfence.bits.hg=1, hv=0 only target TLB entries with V=1 (and not V=0) (https://github.com/chipsalliance/rocket-chip/pull/2954)
• Update Instructions from riscv-opcodes and separate out rocket-specific custom instructions (https://github.com/chipsalliance/rocket-chip/pull/2956, https://github.com/chipsalliance/rocket-chip/pull/2972)
  • post riscv-opcode instruction category scheme at this PR https://github.com/riscv/riscv-opcodes/pull/106
• Decode: switch to using Chisel Decode API (https://github.com/chipsalliance/rocket-chip/pull/2836, https://github.com/chipsalliance/rocket-chip/pull/2994)
• Convert toaxe.py to python3 (https://github.com/chipsalliance/rocket-chip/pull/3034)
• make AsyncClockGroupsKey a node generator (https://github.com/chipsalliance/rocket-chip/pull/2935)
• change debug module name to tlDM (https://github.com/chipsalliance/rocket-chip/pull/3029)
• As part of a larger migration begin refactoring files to chisel3:
  • ALU.scala (https://github.com/chipsalliance/rocket-chip/pull/3039)
  • AMOALU.scala (https://github.com/chipsalliance/rocket-chip/pull/3040)
  • Breakpoint.scala (https://github.com/chipsalliance/rocket-chip/pull/3041)
  • PMP.scala (https://github.com/chipsalliance/rocket-chip/pull/3042)
  • FormalUtils.scala (https://github.com/chipsalliance/rocket-chip/pull/3044)
  • Decode.scala (https://github.com/chipsalliance/rocket-chip/pull/3049)
  • Consts.scala (https://github.com/chipsalliance/rocket-chip/pull/3052)

Fixed

• Proper translation to HRProt3 in AHB Protocol (https://github.com/chipsalliance/rocket-chip/pull/2928/)
• Assert HasFSDirty false (https://github.com/chipsalliance/rocket-chip/pull/2997)
• VSStatus is now read-only and dirty when RoCC is enabled (https://github.com/chipsalliance/rocket-chip/pull/2984)
• RocketCore: avoid false RAW/WAW hazards for integer instructions using an x register whose numeric specifier coincides with a previous instruction's f register. (https://github.com/chipsalliance/rocket-chip/pull/2945)
• Correct rocc_illegal to use reg_vsstatus.xs field (https://github.com/chipsalliance/rocket-chip/pull/2983)
• Zero out aux_pte.reserved_for_future whenever ``aux_pte.ppn` is driven (https://github.com/chipsalliance/rocket-chip/pull/3003)
• Prevent ILTB miss fault PTW thrashing D$ (https://github.com/chipsalliance/rocket-chip/pull/3004)
• Prevent nonsensical use of RVE with Hypervisor (https://github.com/chipsalliance/rocket-chip/pull/2988)
• Explicity outline Rocket's lack of support for haveFSDirty (https://github.com/chipsalliance/rocket-chip/pull/2997)
• Fix bit-width out of range issue when both Sv57 and Hypervisor are enabled (https://github.com/chipsalliance/rocket-chip/pull/3006)
• Fix synthesizability of RoccBlackBox with Vivado (https://github.com/chipsalliance/rocket-chip/pull/3035)

Removed

• Remove Object Model from Diplomacy (https://github.com/chipsalliance/rocket-chip/pull/2967/)
• Removed RegEnable explicit arguments in preparation for changes in Chisel 3.6 (https://github.com/chipsalliance/rocket-chip/pull/2986)
• Removed all mentions of Travis CI and .travis.yml file (https://github.com/chipsalliance/rocket-chip/pull/2647)
• Remove TraceGen from `HeterogeneousTileExampleConfig (https://github.com/chipsalliance/rocket-chip/pull/2923)